The design of networking products has undergone continuous evolution as the speed and functionality of local and wide-area networks have grown. In the early days of packet-based networking, networking devices (such as bridges and routers) were built with a combination of general purpose central processing units (CPUs), discrete logic, and Application Specific Standard Products (ASSPs), including interface controllers and transceivers. The software-based nature of these devices was key to adapting to new protocol standards and the additional functionality required by networks, such as the early Internet. Although these designs were large, complex, and comparatively slow, they met the needs of these early networks, e.g., Ethernet or Token Ring connections.
Over time, as network interface speeds and densities increased, the performance of general-purpose processors fell short of what was needed. This led network vendors to develop simpler, fixed function devices, e.g., Layer 2 Ethernet switches, that could be built with Application Specific Integrated Circuits (ASICs). ASICs traded-off the programmability of software-based designs for hardware-based speed. As ASIC technology progressed, more and more functionality was incorporated into the hardware. This was made possible by protocol consolidation around IP and Ethernet as the dominant enterprise network technology, which reduced the need for product flexibility.
New protocols have developed, e.g., Fibre Channel, ATM/SONET, Gigabit Ethernet, and the like. These protocols have traditionally been implemented with an ASIC and a software layer running on a general-purpose microprocessor. In this traditional implementation, the Fibre Channel ASIC handles all FC-1 layer functions with hardware assists for some FC-2 layer sequence/exchange management.
However, design flexibility without hardware changes are difficult when using ASICs. What is needed is a way of implementing Fibre Channel protocol using a system architecture which is more flexible so as to allow software to be easily adapted to support any upper and lower layer protocols without having the constraint of changing hardware (ASIC) design.